1. Field of the Invention
This invention relates to the use of a Phase-Locked Loop (PLL) in conjunction with a Frequency-Locked Loop (FLL), for use in digital communication systems and other applications.
2. Description of the Prior Art
When sending digital data over relatively long distances from one system to another, the source clock used to transmit the data needs to be recreated at the receiver in order to re-time the data. Using a PLL, or alternatively a PLL combined with a FLL to do this timing recovery is common practice. PLL's are feedback circuits where the phase of an incoming signal is compared to an internal signal using a circuit known as a phase detector. The output of this comparison is fed into the internal signal generator, often called the voltage controlled oscillator (VCO), which then adjusts its frequency to be closer to the incoming frequency. Often the phase detector output is filtered such that the VCO correction does not respond immediately to the latest input. The circuit used to do this filtering is known as a loop filter. A PLL system that uses a loop filter is known as a second order PLL because of the mathematical representation of this feedback system. A PLL system with no loop filter is known as a first order PLL for the same reason.
One consequence of a second-order PLL is that its frequency response to jitter (i.e. phase modulation of the incoming data) can have a magnitude that is greater than unity for some frequency ranges. This is known a jitter peaking, and can have negative consequences in digital communication systems. This is because as data gets passed from one re-timing circuit to the next, the magnitude of the jitter at these frequencies is amplified. This ultimately negatively affects overall system performance. Designers of PLL's used in these types of applications often go to great lengths to insure that their circuit has minimal jitter peaking; see, for example, U.S. Pat. No. 5,036,298. However, this often causes them to make compromises in other aspects of the PLL's performance. A first order PLL has no jitter peaking by definition. However, it has several undesirable characteristics. One is that it can achieve phase lock at an arbitrarily large phase error. This can result in the system being on the edge of losing phase lock, at which point errors in the data received will result. Another undesirable characteristic is that it does not filter high frequency jitter that is on the data. Finally a first order system will have worse data dependent jitter because of the drift in phase that will occur between phase corrections. A second order system can be designed to have near zero phase error, filter out high frequency jitter and have low data dependent jitter.
The addition of an FLL to the PLL, referred to as a FLL/PLL herein, can create a system where the FLL does adjustment to the VCO based on frequency information of the incoming signal compared to the VCO; see, for example, U.S. Pat. No. 4,773,085. A system can be designed using this approach whereby the FLL does the early correction over a relatively wide range of frequencies. This lessens the performance needs of the PLL and can thus make the PLL design job easier. As is further known in the art, PLL's can be built as 1) all analog, 2) mixed analog and digital or 3) all digital. The significant advantage of analog designs, and potentially mixed analog and digital designs, is that they can recover clock at data rates that are very high. But the design and manufacture of analog parts is usually more difficult Also, they can require additional parts on a board such as discrete filter components. The all-digital approach has the advantage that it is easy to design, build and use, although it typically achieves clock recovery at lower data rates than the analog technique.